Dominique Houzet

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This paper proposes a new approach dealing with the tedious problem of NoC guaranteed traffics according to GALS constraints impelled by the upcoming large System-on-Chips with multiclock domains. Our solution has been designed to adjust a tradeoff between synchronous and clockless asynchronous techniques. By means of smart interfaces between synchronous(More)
The first aim of this work is to propose the design of a system-on-chip (SoC) platform dedicated to digital image and signal processing, which is tuned to implement efficiently multiply-and-accumulate (MAC) vector/matrix operations. The second aim of this work is to implement a recent promising neural network method, namely, the support vector machine (SVM)(More)
Faces play an important role in guiding visual attention, and thus, the inclusion of face detection into a classical visual attention model can improve eye movement predictions. In this study, we proposed a visual saliency model to predict eye movements during free viewing of videos. The model is inspired by the biology of the visual system and breaks down(More)
Back-projection (BP) is a costly computational step in tomography image reconstruction such as positron emission tomography (PET). To reduce the computation time, this paper presents a pipelined, prefetch, and parallelized architecture for PET BP (3PAPET). The key feature of this architecture is its original memory access strategy, masking the high latency(More)
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is estimated after RTL synthesis. We propose in this article a methodology based on measurements which allows to model the application power consumption with architectural and algorithmic(More)
High performance computing with low cost machines becomes a reality. As an example, the Sony playstation3 gaming console offers performances up to 150 gflops for a machinepsilas retail price of $400. Unfortunately, higher performances are achieved when the programmer exploits the architectural specificities of its Cell processor: he has to focus on(More)
Graphical Processing Units (GPU) architectures are massively used for resource-intensive computation. Initially dedicated to imaging, vision and graphics, these architectures serve nowadays a wide range of multi-purpose applications. The GPU structure, however, does not suit all applications. This can lead to performance shortage. Among several(More)
model (UML [10]), graphical finite state machine design environments (e.g StateCharts [11]), DSP graphical programming environments (e.g. Ptolemy [8]), or from synchronous programming languages (e.g Esterel [12]). A software generation from a high level model of operating system is proposed by several authors [13-16]. In [15], a software generation from(More)
Nowadays, it is possible to build a multi-GPU supercomputer, well suited for implementation of digital signal processing algorithms, for a few thousand dollars. However, to achieve the highest performance with this kind of architecture, the programmer has to focus on inter-processor communications, tasks synchronization. In this paper, we propose a high(More)
Network on chip (NoC) using packet switching is a solution to cope with complex system on chip (SoC) communications. However, tools are needed to help designers to deal with NoC. The two elements composing an NoC are its routers and its network interfaces (NI). We focus on the specification and generation steps of the /spl mu/spider NOC design flow that(More)