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Wideband receivers are required for many applications including the upcoming software-defined radio (SDR) architectures and ultra-wideband communication standards [1-3]. These standards cover a frequency spectrum from a few hundred MHz up to 6GHz. Co-operability with other communication devices (e.g., cellular and WLAN) operating in the same spectrum is(More)
This paper describes a 2.4GHz Wake-up Receiver (WuRx) designed to operate with low-accuracy (<0.5%) frequency references [1], enabling crystal-less and thus low-cost wireless sensor nodes (WSNs). Robustness to frequency error is achieved by combining non-coherent energy detection with a broadband-IF superheterodyne architecture, and by using a(More)
This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from –70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors(More)
A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DAC). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and(More)
—This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz—ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a(More)
The design of a Duty-Cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately-accurate low-power high-frequency synthesizer suitable for use in nodes for Wireless Sensor Networks (WSN) applications. Thanks to a dual loop configuration the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to(More)