Dmitry Yu. Volkanov

Learn More
In this paper we present a technology for integration of distributed real-time embedded systems (RTES) based on hardware-in-the loop simulation. The environment to support this technology is described. This environment also enables simulation-based evaluation of RTES architecture on early stages of RTES development.
Problems of analysis and design of embedded real-time systems for controlling complex engineering systems are considered by an example of a DYANA simulation environment and its development at the Laboratory of Computing Systems (LCS), Faculty of Computational Mathematics and Cybernetics, Moscow State University. Special attention is paid to the verification(More)
To verify real-time properties of UML statecharts one may apply a UPPAAL, toolbox for model checking of real-time systems. One of the most suitable ways to specify an operational semantics of UML statecharts is to invoke the formal model of Hierarchical Timed Automata. Since the model language of UPPAAL is based on Networks of Timed Automata one has to(More)
In this paper we present DYANA, an HLA-based hardware-in-the-loop simulation tool. This tool is used for distributed Real-Time Embedded Systems (RTES) simulation. RTES models are described by Unified Modeling Language (UML) statechart diagrams. The statechart diagram is transformed into HLA-based Simulation Model (HSM). After translation into HSM we use(More)
In this paper we present DYANA, an HLA-based hardware-in-the-loop simulation tool. This tool is used for distributed Real-Time Embedded Systems (RTES) simulation. RTES models are described by Unified Modeling Language (UML) statechart diagrams. The statechart diagram is transformed into HLA-based Simulation Model (HSM). After translation into HSM we use(More)
Checking the correctness of distributed systems is one of the most difficult and urgent problems in software engineering. A combined toolset for the verification of real-time distributed systems (RTDS) is described. RTDSs are specified as statecharts in the Universal Modeling Language (UML). The semantics of statecharts is defined by means of hierarchical(More)
  • 1