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Go Ahead: A Partial Reconfiguration Framework
TLDR
The tool Go Ahead is introduced that is able to implement run-time reconfigurable systems for all recent Xilinx FPGAs and provides a scripting interface and all features can be accessed remotely.
FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting
TLDR
This paper analyses different hardware sorting architectures in order to implement a highly scaleable sorter for solving huge problems at high performance up to the GB range in linear time complexity and demonstrates how partial run-time reconfiguration can be used for saving almost half the FPGA resources or alternatively for improving the speed.
ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS
TLDR
The ReCoBus-builder tool chain is presented that simplifies the generation of dynamically reconfigurable systems to almost a push-button process and bitstream linking can further be used to speed up the design process of static only systems by eliminating long synthesis runs or place and route steps.
The Xilinx Design Language (XDL): Tutorial and use cases
TLDR
This paper will provide documentation on the Xilinx Design Language and reveal several use cases for this language, which can be used to constrain systems or to directly implement modules or macros forXilinx FPGAs.
BITMAN: A tool and API for FPGA bitstream manipulations
TLDR
The capabilities, API and performance evaluation of BitMan are described, which includes high-level commands such as cutting out regions of a bitstream and placing or relocating modules on an FPGA as well as low- level commands for modifying primitives and for routing clock networks or rerouting signal connections at run-time.
High Speed Partial Run-Time Reconfiguration Using Enhanced ICAP Hard Macro
TLDR
By adding custom logic around the Internal Configuration Access Port (ICAP) to implement an enhanced ICAP hard macro, this paper will investigate the partial run-time reconfiguration speed and explore the limits of the ICAP interface.
Parallel Hardware Merge Sorter
TLDR
A 32-port parallel merge-tree that merges 32 sequences is implemented in a Virtex-7 FPGA and significantly improves its area and speed scalability by allowing stalls and variable sorting rate.
A Survey on FPGA Virtualization
TLDR
This survey identifies and classify the various techniques and approaches for FPGA virtualization into three main categories: 1)Resource level, 2)Node level, and 3)Multi-node level.
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
TLDR
This paper systematically extends the concept of checkpointing known from software systems to hardware tasks running on reconfigurable devices and reveals a tool that takes over the burden of modifying hardware modules for checkpointing.
Resource Elastic Virtualization for FPGAs Using OpenCL
TLDR
The concept of resource elastic virtualization which allows shrinking and growing of accelerators in the spatial domain with the help of partial reconfiguration is introduced which can serve multiple applications simultaneously on the same FPGA and optimize the resource utilization and consequently the overall system performance.
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