Learn More
Accelerator-based systems are making rapid inroads into becoming platforms of choice for high end cloud services. There is a need therefore, to move from the current model in which high performance applications explicitly and programmatically select the GPU devices on which to run, to a dynamic model where GPUs are treated as first class schedulable(More)
Among the different methods of reducing power for core-based system-on-chip (SoC) designs, the <i>voltage island technique</i> has gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are the two important steps in the design process. We propose a new application-driven,(More)
Among the different methods of reducing power for core-based system-on-chip (SoC) designs, the <i>voltage-island</i> <i>technique</i> has gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are two important steps in the design process. We propose a new application-driven approach to(More)
While GPUs have become prominent both in high performance computing and in online or cloud services, they still appear as explicitly selected 'devices' rather than as first class schedulable entities that can be efficiently shared by diverse server applications. To combat the consequent likely under-utilization of GPUs when used in modern server or cloud(More)
Recent work on real-world graph analytics has sought to leverage the massive amount of parallelism offered by GPU devices, but challenges remain due to the inherent irregularity of graph algorithms and limitations in GPU-resident memory for storing large graphs. We present GraphReduce, a highly efficient and scalable GPU-based framework that operates on(More)
Current silicon test methods are highly effective at sensitizing and propagating most electrical faults. Unfortunately, with ever increasing chip complexity and shorter time-to-market windows, an increasing number of faults escape undetected. To address this problem, we propose a novel technique to help identify hard-to-find electrical faults that are not(More)
Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90-nm technology with higher leakage currents, it is appropriate to revisit existing design metrics. In this paper, a reevaluation of the metrics is(More)
Exponential increase of online data and a corresponding growth of data-centric applications (Big Data analytics) forces system architects to revisit assumptions and requirements of the future system design. New non-volatile memory (NVM) technologies, such as Phase-Change Memory (PCM) and HP Memristor offer significantly improved latency and power efficiency(More)