Dipanjan Sengupta

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Recent work on real-world graph analytics has sought to leverage the massive amount of parallelism offered by GPU devices, but challenges remain due to the inherent irregularity of graph algorithms and limitations in GPU-resident memory for storing large graphs. We present GraphReduce, a highly efficient and scalable GPU-based framework that operates on(More)
Among the different methods of reducing power for core-based system-on-chip (SoC) designs, the <i>voltage island technique</i> has gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are the two important steps in the design process. We propose a new application-driven,(More)
Accelerator-based systems are making rapid inroads into becoming platforms of choice for high end cloud services. There is a need therefore, to move from the current model in which high performance applications explicitly and programmatically select the GPU devices on which to run, to a dynamic model where GPUs are treated as first class schedulable(More)
While GPUs have become prominent both in high performance computing and in online or cloud services, they still appear as explicitly selected 'devices' rather than as first class schedulable entities that can be efficiently shared by diverse server applications. To combat the consequent likely under-utilization of GPUs when used in modern server or cloud(More)
In the nanometer era of VLSI design, high power consumption is considered to be a &#x201C;show-stopper&#x201D; for many applications. Voltage Island design has emerged as a popular method for addressing this issue. This technique requires multiple supply voltages on the same chip with blocks assigned to different supply voltages. Implementation challenges(More)
With the growing complexity of current designs and shrinking time-to-market, traditional ATPG methods fail to detect all electrical faults in the design. Debug teams have to spend considerable amount of time and effort to identify these faults during post silicon debug. This work proposes off-chip analysis to speed-up the effort of identifying hard-to-find(More)
The synthesis and SAR of a novel 3-benzazepine series of 5-HT2C agonists is described. Compound 7d (lorcaserin, APD356) was identified as one of the more potent and selective compounds in vitro (pEC50 values in functional assays measuring [(3)H]phosphoinositol turnover: 5-HT2C = 8.1; 5-HT2A = 6.8; 5-HT2B = 6.1) and was potent in an acute in vivo rat food(More)
We report on the synthesis, biological evaluation and structure-activity relationships for a series of 3-benzazepine derivatives as 5-HT(2C) receptor agonists. The compounds were evaluated in functional assays measuring [3H] phosphoinositol turnover in HEK-293 cells transiently transfected with h5-HT(2C), h5-HT(2A) or h5-HT(2B) receptors. Several compounds(More)
Two series of fused tricyclic indoles were identified as potent and selective S1P(1) agonists. In vivo these agonists produced a significant reduction in circulating lymphocytes which translated into robust efficacy in several rodent models of autoimmune disease. Importantly, these agonists were devoid of any activity at the S1P(3) receptor in vitro, and(More)