Dionysios Kouroussis

Learn More
Design verification must include the power grid. Checking that the voltage on the power grid does not drop by more than some critical threshold is a very difficult problem, for at least two reasons: <i>i)</i> the obviously large size of the power grids for modern high-performance chips, and <i>ii)</i> the difficulty of setting up the right simulation(More)
To ensure reliable performance of a chip, design verification of the power grid is of critical importance. This paper builds on previous work that models the working behavior of the circuit in terms of abstracted current constraints and solves for worst-case voltage drop on the grid as a linear program. The main motivation is to allow the efficient(More)
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low or high. This analysis may not give the true maximum delay of a circuit because it neglects the possible mismatch between drivers and loads. We propose a new approach for timing(More)
—Static timing analysis (STA) techniques allow a designer to check the timing of a circuit at different process corners, which typically include corner values of the supply voltages as well. Traditionally, however, this analysis only considers cases where the supplies are either all low or all high. As will be demonstrated , this may not yield the true(More)
  • 1