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Abstraction Techniques for Validation Coverage Analysis and Test Generation

• Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote
• IEEE Trans. Computers
• 1998

ion Techniques for Validation Coverage Analysis and Test Generation 1 Dinos Moundanos Jacob A. Abraham Computer Engineering Research Center The University of Texas at Austin ENS 424 Austin, TX 78712… (More)

Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors

• Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham
• ICCD
• 1995

A Unified Framework for Design Validation and Manufacturing Test

• Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote
• ITC
• 1996

New approaches to address the diicult problems in test are necessary if its current status as a major bottleneck in the production of quality integrated circuits is to be changed. In this paper we… (More)

A new scheme to compute variable orders for binary decision diagrams

• Jawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell
• Great Lakes Symposium on VLSI
• 1994

In this paper we introduce some new methods using which importance of a variable in a Boolean function can be computed. Such methods can easily be used for computing variable order to construct BDDs.… (More)

Efficient variable ordering and partial representation algorithm

• Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross
• VLSI Design
• 1995

In this paper we introduce some new methods for constructing Ordered Partial Decision Diagrams (0P.DDs). The algorithms are effective in capturing a signi$cant fraction of a given function’s truth… (More)

Distributed Binary Decision Diagrams for Verification of Large Circuit

• Prakash Arunachalam, Craig M. Chase, Dinos Moundanos
• ICCD
• 1996

Below you will find readings to be presented in class by the students. You must select a paper (or papers, if multiple ones are listed on the same line), then send an email to request it. If nobody… (More)

Formal Checking of Properties in Complex Systems Using Abstractions

• Dinos Moundanos, Jacob A. Abraham
• Great Lakes Symposium on VLSI
• 1999

Only very small designs can be verified currently using property checking due to state-space explosion. Abstractions have been developed to simplify the design in an attempt to address this problem.… (More)

Using Verification Technology for Validation Coverage Analysis and Test Generation

• Dinos Moundanos, Jacob A. Abraham
• VTS
• 1998

Despite great advances in Formal Veri cation (FV), simulation is still the primary means for design validation. The de nition of pragmatic measures for the coverage achieved and the problem of… (More)

Eecient Variable Ordering and Partial Representation Algorithms

• Dinos Moundanos, Jim Bitner, Jacob A. Abraham, Donald S. Fussell, Dianne Rossy
• 1995

In this paper we introduce some new methods for constructing Ordered Partial Decision Diagrams (OPDDs). The algorithms are eeective in capturing a signiicant fraction of a given function's truth… (More)

Analysis of composition complexity and how to obtain smaller canonical graphs

• Jawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu
• DAC
• 2000

We discuss an open problem in construction of Reduced Ordered Binary Decision Diagrams (ROBDDs) using composition, and prove that the worst case complexity of the construction is truly cubic. With… (More)

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