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- Publications
- Influence

Abstraction Techniques for Validation Coverage Analysis and Test Generation

- Dinos Moundanos, J. Abraham, Yatin Vasant Hoskote
- Computer Science
- IEEE Trans. Computers
- 1998

The enormous state spaces which must be searched when verifying the correctness of, or generating tests for, complex circuits precludes the use of traditional approaches. Hard-to-find abstractions… Expand

Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors

- Yatin Vasant Hoskote, Dinos Moundanos, J. Abraham
- Computer Science
- Proceedings of ICCD '95 International Conference…
- 2 October 1995

Simulation is still the primary, although inadequate, resource for verifying the conformity of a design to its functional specification. Fortunately, most errors in the early stages of design involve… Expand

Eecient Variable Ordering and Partial Representation Algorithms

In this paper we introduce some new methods for constructing Ordered Partial Decision Diagrams (OPDDs). The algorithms are eeective in capturing a signiicant fraction of a given function's truth… Expand

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A unified framework for design validation and manufacturing test

- Dinos Moundanos, J. Abraham, Yatin Vasant Hoskote
- Computer Science
- Proceedings International Test Conference . Test…
- 20 October 1996

New approaches to address the difficult problems in test are necessary if its current status as a major bottleneck in the production of quality integrated circuits is to be changed. The authors… Expand

Distributed binary decision diagrams for verification of large circuits

- P. Arunachalam, C. Chase, Dinos Moundanos
- Computer Science
- Proceedings International Conference on Computer…
- 7 October 1996

Binary Decision Diagrams (BDDs) are widely used for efficiently representing logic designs and for verifying their equivalence. However, they often require large amounts of memory even for relatively… Expand

Using verification technology for validation coverage analysis and test generation

- Dinos Moundanos, J. Abraham
- Computer Science
- Proceedings. 16th IEEE VLSI Test Symposium (Cat…
- 26 April 1998

Despite great advances in Formal Verification (FV) simulation is still the primary means for design validation. The definition of pragmatic measures for the coverage achieved and the problem of… Expand

Analysis of composition complexity and how to obtain smaller canonical graphs

- J. Jain, K. Mohanram, Dinos Moundanos, I. Wegener, Y. Lu
- Mathematics, Computer Science
- Proceedings 37th Design Automation Conference
- 1 June 2000

We discuss an open problem in construction of Reduced Ordered Binary Decision Diagrams (ROBDDs) using composition, and prove that the worst case complexity of the construction is truly cubic. With… Expand

Efficient variable ordering and partial representation algorithm

- J. Jain, Dinos Moundanos, J. Bitner, J. Abraham, D. Fussell, D. Ross
- Computer Science
- Proceedings of the 8th International Conference…
- 4 January 1995

In this paper we introduce some new methods for constructing Ordered Partial Decision Diagrams (OPDDs), The algorithms are effective in capturing a significant fraction of a given function's truth… Expand

A new scheme to compute variable orders for binary decision diagrams

- J. Jain, J. Bitner, Dinos Moundanos, J. Abraham, D. Fussell
- Computer Science
- Proceedings of 4th Great Lakes Symposium on VLSI
- 4 March 1994

Introduces some new methods for estimating the "importance" of a variable in a Boolean function, and uses them to compute variable orders for OBDD construction. These measures are based on… Expand

On Design Validation Using Verification Technology

- Dinos Moundanos, J. Abraham
- Computer Science
- J. Electron. Test.
- 1 August 1999

Despite great advances in the area of Formal Verification during the last ten years, simulation is currently the primary means for performing design verification. The definition of an accurate and… Expand