Ding-Siang Su

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This paper proposes a reconfigurable multi-core architecture, called <i>hyperscalar</i> that enables many scalar cores to be united dynamically as a larger superscalar processor to accelerate a thread. To accomplish this, we propose the virtual shared register files (VSRF) that allow the instructions of a thread executed in the united cores to logically(More)
This paper proposes a unitable multi-core architecture, called hyperscalar, that can dynamically unite many scalar cores as a larger superscalar processor to accelerate a thread. To accomplish this, this paper proposes the virtual shared register files (VSRFs) that help the instructions of a thread in different cores can logically face a uniform set of(More)
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