Dinesh P. Mehta

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We present two practical algorithms for partitioning circuit components represented by rectilinear polygons so that they can be stored using the L-shaped corner stitching data structure; that is, our algorithms decompose a simple polygon into a set of nonoverlapping L-shapes and rectangles by using horizontal cuts only. The more general of our algorithms(More)
VII. CONCLUSION We present a simultaneous buffer insertion/sizing and wire sizing zero skew clock-tree optimization algorithm, ClockTune. The algorithm takes polynomial runtime and memory usage and finds minimum-delay and minimum-power embeddings efficiently. For wire widths from 0.3 to 3 m and buffer widths from 1 2 to 10 2, the algorithm achieves 45 2(More)
This paper presents three minimum-area floorplanning algorithms that use flexible arbitrary rectilinear shapes for the standard cell regions in MBC design. The first algorithm (pure HCST) introduces a grid traversal technique which guarantees a minimum-area floorplan. The second algorithm (Hybrid-BF) uses a combination of HCST and Breadth First (BF)(More)
Automated reaction mapping is a fundamental first step in the analysis of chemical reactions and opens the door to the development of sophisticated chemical kinetic tools. This article formulates the reaction mapping problem as an optimization problem. The problem is shown to be NP-Complete for general graphs. Five algorithms based on canonical graph naming(More)
Decision trees are popular representations of Bool-ean functions. We show that, given an alternative representation of a Boolean function , say as a read-once branching program, one can find a decision tree Ì which approximates to any desired amount of accuracy. Moreover, the size of the decision tree is at most that of the smallest decision tree which can(More)
A productivity-driven methodology for incremental floorplanning is described and the <italic>constrained polygon transformation problem</italic>, a key step of this methodology, is formulated. The input to the problem consists of a floorplan computed using area estimates and the actual area required for each subcircuit of the floorplan. Informally, the(More)