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The contribution of this paper is twofold. We firstly show that an augmented diminished-1 adder can be used for the modulo 2<sup>n</sup> +1 addition of two n-bit operands in the weighted representation, if it is driven by operands whose sum has been decreased by 1. This scheme outperforms solutions that are based on the use of binary adders and/or weighted(More)
In this paper we show that an accumulator can be modified to behave as a Non-Linear Feedback Shft Register suitable for test response compaction. The hardware required for this modification is less than that required to mod& a register to a Multiple Input Linear Feedback Shgt Register, MISR. We show with experiments on ISCAS'85, ISCAS'89 benchmark circuits(More)
The low power as a feature of a BIST scheme is a significant target due to quality as well as cost related issues. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power Built In Self Test (BIST) scheme for them. We propose(More)
This paper presents a novel test vector ordering method for average power consumption minimization. The proposed method orders the test vectors taking into account the expected switching activity at the primary inputs and at a very small set of internal lines of the circuit under test. The computational time required by the proposed method is very small(More)
Image edge detection plays a fundamental role in image processing as well as in computer and machine vision while when applied in medical images can improve medical diagnosis. Thus, efficient hardware implementation of an edge detection system is highly appreciated. In this work we propose a novel architecture for image filtering and edge detection using(More)
In this paper we propose a new algorithm for seeds selection in LFSR-based test-per-clock BIST. The proposed algorithm uses the well-known concept of solving systems of linear equations and, based on heuristics, minimizes the number of seeds and test vectors while achieving 100% fault coverage. Experimental results indicate that it compares favorably to the(More)
Test vector ordering with vector repetition has been presented as a method to reduce the average as well as the peak power dissipation of a circuit during testing. Based on this method, in this paper we present some techniques that can be used to further reduce the average power dissipation. Experimental results validate that the proposed techniques achieve(More)
In this paper we present a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jumps from a state to the required state (seed) by inverting the logic value of some of the bits of its next state. An eflcient(More)