Dimitris Bakalis

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The contribution of this paper is twofold. We firstly show that an augmented diminished-1 adder can be used for the modulo 2<sup>n</sup> +1 addition of two n-bit operands in the weighted representation, if it is driven by operands whose sum has been decreased by 1. This scheme outperforms solutions that are based on the use of binary adders and/or weighted(More)
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the(More)
This paper presents a novel test vector ordering method for average power consumption minimization. The proposed method orders the test vectors taking into account the expected switching activity at the primary inputs and at a very small set of internal lines of the circuit under test. The computational time required by the proposed method is very small(More)
In this paper we propose a new algorithm for seeds selection in LFSR-based test-per-clock BIST. The proposed algorithm uses the well-known concept of solving systems of linear equations and, based on heuristics, minimizes the number of seeds and test vectors while achieving 100% fault coverage. Experimental results indicate that it compares favorably to the(More)
In this paper we show that an accumulator can be modified to behave as a Non-Linear Feedback Shft Register suitable for test response compaction. The hardware required for this modification is less than that required to mod& a register to a Multiple Input Linear Feedback Shgt Register, MISR. We show with experiments on ISCAS’85, ISCAS’89 benchmark circuits(More)
Power dissipation during scan-based testing has gained significant importance in the past few years. In this work we examine the use of transition frequency based on scan cell ordering techniques in pseudorandom scan based BIST in order to reduce average power dissipation. We also propose the resetting of the input register of the circuit together with(More)
The diminished-one representation has been proposed for RNS-based systems with moduli of the 2^n+1 forms as an encoding that is more efficient than the normal representation in the arithmetic processing units. However, its use necessitates a two-step reverse conversion, in which a diminished-to-normal conversion is first performed before the final(More)
In this paper we present a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jumps from a state to the required state (seed) by inverting the logic value of some of the bits of its next state. An eflcient(More)
We present Eudoxus, a tool for generation of architectural variants for arithmetic soft cores and testing structures targeting a wide variety of functions, operand sizes and architectures. Eudoxus produces structural and synthesizable VHDL and/or Verilog descriptions for: (a) several arithmetic operations including addition, subtraction, multiplication,(More)