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NBTI-aware data allocation strategies for scratchpad memory based embedded systems
While performance and power continue to be important metrics for embedded systems, as CMOS technologies continue to shrink, new metrics such as variability and reliability have emerged as limitingExpand
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Edge-TM
TLDR
We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a Hardware Transactional Memory (HTM)-based error recovery mechanism. Expand
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Speculative synchronization for coherence-free embedded NUMA architectures
TLDR
In this paper, we present a new scheme for hardware transactional memory support within a cluster-based NUMA system that lacks an underlying cache-coherence protocol. Expand
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Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution
TLDR
We propose a novel scheme that allows to dynamically adjust to an evolving COP and operate at highly reduced margins, while guaranteeing forward progress. Expand
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Flexible data allocation for scratch-pad memories to reduce NBTI effects
TLDR
In this paper, we proposed a software-directed memory allocation technique, which offers a valuable solution to the NBTI-induced aging in SPMs. Expand
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Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems
TLDR
We propose Embedded-Spec, a hardware solution for supporting transparent lock speculation, without the requirement for special supporting instructions. Expand
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Evaluating critical bits in arithmetic operations due to timing violations
TLDR
We examine the architecture of FPUs and design a new error model, which we call Critical Bit, which can be derived from architectural implementations of floating point arithmetic units. Expand
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NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems
TLDR
The push to embed reliable and low-power memories architectures into modern systems-on-chip is driving the EDA community to develop new design techniques and circuit solutions that can concurrently optimize aging effects due to Negative Bias Temperature Instability (NBTI), and static power consumption due to leakage mechanisms. Expand
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Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems
TLDR
We present thrifty-malloc: a transaction-friendly dynamic memory manager for high-end embedded multicore systems. Expand
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Flexibl eDat aAllocatio nfo rScratch-pa dMemorie st oReduc eNBTI Effects
Negative Bias Temperature Instability (NBTI) is a major reliability issue in nanoscale VLSI sys- tems. Previous work has shown how the exploitation of conventional optimization techniques can reduceExpand