Dileepan Joseph

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Logarithmic cameras have the wide dynamic range required to image natural scenes and encode the important contrast information within the scene. However, the images from these cameras are severely degraded by fixed pattern noise. Previous attempts to improve the quality of images from these cameras by removing additive fixed pattern noise have lead to(More)
Logarithmic CMOS image sensors capture high dynamic range scenes without saturation or loss of perceptible detail but problems exist with image quality. This thesis develops and applies methods of modelling and calibration to understand and improve the fixed pattern noise (FPN) and colour rendition of logarithmic imagers. Chapter 1 compares CCD and CMOS(More)
Wide dynamic range logarithmic imagers can render naturally illuminated scenes while preserving detail and contrast information at a lower cost than high dynamic range linear sensors. However, the quality of the output is severely degraded by fixed pattern noise (FPN). Although previous FPN correction techniques can eliminate the dominant additive form of(More)
The quality of the output images from high dynamic range logarithmic sensors is limited by fixed pattern noise (FPN) which is caused by device mismatches within pixels in an array. It leads to inferior image quality in comparison to images from other sensors of similar resolution. Previous design and post-chip attempts to correct this type of noise, have(More)
All things considered, electronic imaging systems do not rival the human visual system despite notable progress over 40 years since the invention of the CCD. This work presents a method that allows design engineers to evaluate the performance gap between a digital camera and the human eye. The method identifies limiting factors of the electronic systems by(More)
A delta-sigma analog-to-digital-converter (ADC) is designed, optimized and simulated for column-level data conversion in a CMOS image sensor. For a 0.18μm process, the design achieves 80dB of signal-to-noise ratio (SNR), including a 10dB margin for kTC noise not simulated, and consumes 210μW of power at a 50kHz sampling rate. Low power is realized mainly by(More)
Area and power optimization of a first-order deltasigma analog-to-digital converter (ADC) for pixel-level data conversion is presented. The ADC is designed for use in a verticallyintegrated logarithmic CMOS image sensor. A switched-capacitor modulator with minimum area has been employed. Unlike other similar structures, the decimation is performed inside(More)
Logarithmic CMOS image sensors encode a high dynamic range scene in a manner that roughly approximates human perception whereas linear sensors with equivalent quantization suffer from saturation or loss of detail. Moreover, the continuous response of logarithmic pixels permit high frame rates and random access, features that are useful in motion detection.(More)