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Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the author. Abstract Logarithmic CMOS image(More)
Logarithmic cameras have the wide dynamic range required to image natural scenes and encode the important contrast information within the scene. However, the images from these cameras are severely degraded by fixed pattern noise. Previous attempts to improve the quality of images from these cameras by removing additive fixed pattern noise have lead to(More)
—Wide dynamic range logarithmic imagers can render naturally illuminated scenes while preserving detail and contrast information at a lower cost than high dynamic range linear sensors. However, the quality of the output is severely degraded by fixed pattern noise (FPN). Although previous FPN correction techniques can eliminate the dominant additive form of(More)
All things considered, electronic imaging systems do not rival the human visual system despite notable progress over 40 years since the invention of the CCD. This work presents a method that allows design engineers to evaluate the performance gap between a digital camera and the human eye. The method identifies limiting factors of the electronic systems by(More)
– The quality of the output images from high dynamic range logarithmic sensors is limited by fixed pattern noise (FPN) which is caused by device mismatches within pixels in an array. It leads to inferior image quality in comparison to images from other sensors of similar resolution. Previous design and post-chip attempts to correct this type of noise, have(More)
—Logarithmic CMOS image sensors are appealing for their high-contrast and high-speed response but they require post-processing to achieve high-quality images. Previously published work has explained the fixed pattern noise (FPN) in these image sensors using a steady-state analysis. This paper explains how the transient response of the readout circuit may(More)
— Area and power optimization of a first-order delta-sigma analog-to-digital converter (ADC) for pixel-level data conversion is presented. The ADC is designed for use in a vertically-integrated logarithmic CMOS image sensor. A switched-capacitor modulator with minimum area has been employed. Unlike other similar structures, the decimation is performed(More)
– A delta-sigma analog-to-digital-converter (ADC) is designed , optimized and simulated for column-level data conversion in a CMOS image sensor. For a 0.18µm process, the design achieves 80dB of signal-to-noise ratio (SNR), including a 10dB margin for kTC noise not simulated, and consumes 210µW of power at a 50kHz sampling rate. Low power is realized mainly(More)