Dieter Verhulst

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In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an architecture optimized to handle flow processing tasks such as parsing, classification and packet manipulation. The VLIW instruction set allows for high degree of parallelism among the(More)
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potential bottlenecks. A second design iteration results in a(More)
A procedure is proposed to normalize enzymatic reaction velocities measured in separate experiments. After calculation of the Km and maximum velocity in each individual set of data, the velocities measured in each experiment are reanalyzed by regression analysis with the constraint that they yield a Km identical to the geometric mean of the individual Km's(More)
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