Didier Bouvet

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Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using multiple threshold voltages (<i>V</i><sub>T</sub>), which is enabled by our underlying technology. We(More)
The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuitry that is defined on the lithography scale. In this paper, we evaluate the addressing scheme of the(More)
In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters.(More)
—This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman(More)
This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching (3-10 mV/dec.) as well as hysteresis in both I<sub>D</sub>(V<sub>DS</sub>) and(More)
—This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowires may generate large errors, while being challenging from a technological aspect. Here, we propose(More)
This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5&#x00D7;10<sup>18</sup> atoms/cm<sup>3</sup>. The devices demonstrate up to six decades of I<sub>on</sub>/I<sub>off</sub> ratio and a(More)
We report for the first time the optimization of the channel lateral strain profile as a new technological booster for improved performance of multi-gate n-channel MOSFET. We find that quasi-uniform or flat-Gaussian-close-to-the-drain profiles are optimum for the I<inf>on</inf> boosting of sub-50nm scaled MOSFETs, while the penalty on I<inf>off</inf> and(More)
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