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—This brief presents a detailed time-domain and frequency domain analysis of a direct RF sampling mixer. Design considerations such as incomplete charge sharing and large signal nonlinearity are addressed. An accurate frequency-domain transfer function is derived. Estimation of noise figure is given. The analysis applies to the design of sub-sampling mixers(More)
In this paper, a low supply static 2:1 frequency divider based on 0.13 mum CMOS is presented. It is designed for 40-Gb/s optical communication systems. Current-mode logic (CML) is adopted because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. This frequency divider is designed with output buffer to drive the(More)
This paper presents a novel CMOS edge equalizer for 10-Gb/s transceivers for backplane channels with high loss. The equalizer reduces ISI at edges and ISI at data centers simultaneously without incurring multilevel signaling. Unlike conventional edge equalizer that recovers data from current sample and previous sample, this equalizer recovers data only from(More)
This paper presents detailed analysis of edge based NRZ equalizer proposed in IEEE 802.3ap Task Force. Paradox on spectrum zero at Nyquist frequency is explained. Design methods are improved. Optimization methods are proposed. Results at 10-Gb/s transmission through 2 practical backplanes verify the analysis, design, and optimization methods.
A low supply voltage low phase noise 10-GHz CMOS quadrature LC-VCO (LC-QVCO) is systematically an­ alyzed and designed for low power applications in wireline and wireless communication systems. Using a semi-empirical model, the impacts on VCO oscillation magnitude, loaded quality factor (Qloaded), and oscillation frequency from the parasitic components of(More)
In this paper, a decision circuit based on 0.13 mum CMOS is presented. It is designed for 40-Gb/s optical communication systems. This decision circuit achieved by master-slave flip-flops (MS-FFs) with opposite clock can operate at a bit rate of 40-Gb/s and beyond. Current-mode logic (CML) is adopted due to the higher speed compared to static CMOS and the(More)
This paper presents an integrated modeling, simulation and analysis technique for high-speed serial link transceiver over band-limited channel. The Verilog-A behavioral modeling blocks, transistor-level circuits based on the BSIM models, and the backplane channel with .s4p format model were simulated simultaneously in Cadence Spectre environment. The output(More)
This paper presents a programmable pre-cursor ISI equalization circuit for high-speed serial data transmission over highly lossy electrical backplane channels. Although decision-feedback-equalizer (DFE) provides an effective way to compensate various channel impairments, such as frequency dependent loss, dispersion and reflections in the legacy backplane(More)
A number of simulation methods dealing with measured S-parameters have been developed for the simulation of high-speed backplane transceivers and printed circuit board signal integrity analysis. Although these methods implemented in many circuit simulators provide correct system-level and transistor-level simulations, they usually fail to give correct(More)