Dianyong Chen

Learn More
This brief presents a detailed time-domain and frequency-domain analysis of a direct RF sampling mixer. Design considerations such as incomplete charge sharing and large signal nonlinearity are addressed. An accurate frequency-domain transfer function is derived. Estimation of noise figure is given. The analysis applies to the design of sub-sampling mixers(More)
In this paper, a low supply static 2:1 frequency divider based on 0.13 mum CMOS is presented. It is designed for 40-Gb/s optical communication systems. Current-mode logic (CML) is adopted because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. This frequency divider is designed with output buffer to drive the(More)
This paper presents detailed analysis of edge based NRZ equalizer proposed in IEEE 802.3ap Task Force. Paradox on spectrum zero at Nyquist frequency is explained. Design methods are improved. Optimization methods are proposed. Results at 10-Gb/s transmission through 2 practical backplanes verify the analysis, design, and optimization methods.
This paper presents a novel CMOS edge equalizer for 10Gb/s transceivers for backplane channels with high loss. The equalizer reduces ISI at edges and ISI at data centers simultaneously without incurring multilevel signaling. Unlike conventional edge equalizer that recovers data from current sample and previous sample, this equalizer recovers data only from(More)
This paper presents a 10-Gb/s backplane transmitter with a finite impulse response (FIR) pre-emphasis equalizer to suppress inter-symbol-interference (ISI) at data centers and transition edges simultaneously. The design concepts are discussed. Circuits in 0.13µm IBM CMOS technologies are given. Comparison with conventional data center oriented(More)
This paper presents a programmable pre-cursor ISI equalization circuit for high-speed serial data transmission over highly lossy electrical backplane channels. Although decision-feedback-equalizer (DFE) provides an effective way to compensate various channel impairments, such as frequency dependent loss, dispersion and reflections in the legacy backplane(More)
In this paper, a decision circuit based on 0.13 mum CMOS is presented. It is designed for 40-Gb/s optical communication systems. This decision circuit achieved by master-slave flip-flops (MS-FFs) with opposite clock can operate at a bit rate of 40-Gb/s and beyond. Current-mode logic (CML) is adopted due to the higher speed compared to static CMOS and the(More)
This paper presents an integrated modeling, simulation and analysis technique for high-speed serial link transceiver over band-limited channel. The Verilog-A behavioral modeling blocks, transistor-level circuits based on the BSIM models, and the backplane channel with .s4p format model were simulated simultaneously in Cadence Spectre environment. The output(More)
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6µm CMOS. The implemented CDR comprises a phase-and frequency-locked loop using an I/Q ring VCO to recover clock from incoming non-return-to-zero (NRZ) data stream and a data decision circuit to retime the received data,(More)