Diana Hecht

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Due to advances in fiber-optics and VLSI technology, interconnection networks that allow multiple simultaneous broadcasts are becoming feasible. Distributed-shared-memory implementations on such networks promise high performance even for applications with small granularity. This paper presents the architecture of one such implementation, called the(More)
In this paper, we describe new protocols augmenting traditional cache coherency mechanisms to implement fault-tolerance based on Recovery Blocks and checkpointing. Concurrent processes compound rollback recovery since the rollback can potentially lead to a "domino-effect" whereby the process is rolled back to the beginning. Several approaches have been(More)
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes without contention, and can efficiently interconnect over one hundred nodes. Each node has a dedicated output channel and an array of receivers, with one receiver dedicated to every(More)
— Data cache misses reduce the performance of wide-issue processors by stalling the data supply to the processor. It is especially worse in the DSM environment. Prefetching data for the critical data address misses is one way to tolerate the cache miss latencies. But current applications with irregular access patterns make it difficult to prefetch data(More)
Due to advances in fiber-optics and VLSI technology, interconnection networks which allow multiple simultaneous broadcasts are becoming feasible. This paper summarizes one such multiprocessor architecture called the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus). It also presents the design of the network interface and the cache and directory(More)
ii Dedications I dedicate this dissertation to my husband, Stephen. I would not have been able to achieve this goal without his faith in me and his sacrifice, patience, and understanding. iii Acknowledgements I would like to give a special thanks to my advisor, Dr Constantine Katsinis, for his invaluable guidance, encouragement, advice and friendship over(More)
In this paper we describe the results of our simulation analysis of a high-performance processing architecture based on the RapidIO network protocol. RapidIO is a 10 Gb/s, low-latency packet-switched interconnect technology designed for processor-to-processor, processor-to-memory, and processor-to-peripheral interconnects. Two network topologies were(More)
Due to advances in fiber-optics and VLSI technology, interconnection networks which allow multiple simultaneous broadcasts are becoming feasible. This paper summarizes one such multiprocessor architecture called the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus). It also presents enhancements to the network interface and the cache and directory(More)