Dhruva Ghai

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— This paper proposes a novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs). A nano-CMOS current-starved voltage controlled oscillator (VCO) circuit has been designed using this flow as a case study. The oscillation frequency is considered as the objective optimization function with the area overhead as(More)
A novel design approach for simultaneous power and stability (static noise margin, SN M) optimization of nano-CMOS static random access memory (SRAM) is presented. A 45nm single-ended seven transistor SRAM is used as a case study. The SRAM is subjected to a dual-V T h assignment using a novel combined Design of Experiments and Integer Linear Programming(More)
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A current-starved voltage controlled oscillator (VCO) is treated as a case study and to the best of the authors' knowledge, this is the first VCO design that accounts for both parasitic degradation(More)
We propose a novel design flow for mismatch and process-variation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is designed using the proposed methodology for 32nm CMOS technology. Performance metrics such as power, output voltage swing, dynamic range (DR) and capture time (delay) have been(More)
4 Welcome Welcome to the 24th edition of the Great Lakes Symposium on VLSI (GLSVLSI) 2014 held in Houston, Texas. GLSVLSI is a premier venue for the dissemination of manuscripts of the highest quality BLOCKINin BLOCKINall BLOCKINareas BLOCKINrelated BLOCKINto BLOCKINVLSI, BLOCKINdevices BLOCKINand BLOCKINsystem BLOCKINlevel BLOCKINdesign. BLOCKINThe(More)
• Level Converters are becoming overhead for the circuits they are employed in. If their power consumption continues to grow they will The ULC consists of input voltage Dynamic Power (P dynamic) S b th h ld L k ULC Characterization power consumption continues to grow, they will fail to serve their purpose. • We propose the application of a dual-Tox(More)
In this paper, we present the design of a P4 (Power-Performance-Process-Parasitic) aware voltage controlled oscillator (VCO) at nano-CMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance (center frequency) of the VCO. For process variation analysis, we propose a methodology called Design(More)
— The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This(More)
and Conclusions  A novel design flow is presented for simultaneous P3 (power minimization, performance maximization and process variation tolerance) optimization of nano-CMOS circuits.  For demonstration of the effectiveness of the flow, a 45 nm single-ended 7-transistor SRAM is used as example circuit.  The SRAM cell is subjected to a dual-V Th(More)