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In this paper, a 6-bit 1 Gs/sec flash analog-to-digital converter (ADC) for low voltage and high speed system-on-chip (SoC) applications is presented. Simulated with the 45nm Predictive Technology Model, the results demonstrate INL < 0.5LSB, DNL < 0.8LSB and a signal to noise and distortion ratio of 31.9dB. The Threshold Inverter Quantization (TIQ)(More)
This paper presents a process variation tolerant, SoC ready, 1 GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologies. The physical design is carried out with a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit using Design for Manufacturability (DFM) methodologies.(More)
This paper proposes a novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs). A nano-CMOS current-starved voltage controlled oscillator (VCO) circuit has been designed using this flow as a case study. The oscillation frequency is considered as the objective optimization function with the area overhead as(More)
• At nanoscale technologies, process variations have significant impact on VCO Logical Design Final Optimized layout of the VCO ), ( 2 5 n n p p ox tot L W L W C C + = circuit performance and need to be included in the design cycle. RLCK parasitics cause further performance degradations. • We present a parasitic aware, process variation tolerant design(More)
A novel design approach for simultaneous power and stability (static noise margin, SNM ) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-ended seven transistor SRAM is used as a case study. The SRAM is subjected to a dual-VTh assignment using a novel combined Design of Experiments and Integer Linear Programming(More)
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is designed using the proposed methodology for 32nm CMOS technology. Performance metrics such as power, output voltage swing, dynamic range (DR) and capture time (delay) have been(More)
• Level Converters are becoming overhead for the circuits they are employed in. If their power consumption continues to grow they will The ULC consists of input voltage ULC Transistor Level Design Total Power Dissipation in the ULC circuit (PULC) Dynamic Power (Pdynamic) S b th h ld L k ULC Characterization , fail to serve their purpose. • We propose the(More)
In this paper, a novel design flow is presented for simultaneous P3 (power minimization, performance maximization and process variation tolerance) optimization of nano-CMOS circuits. For demonstration of the effectiveness of the flow, a 45nm single-ended 7-transistor SRAM is used as example circuit. The SRAM cell is subjected to a dual-VTh assignment based(More)
In this paper, a novel design flow is presented for power minimization of nano-CMOS SRAM (static random access memory) circuits, while maintaining their performance. A 32nm high-K/metalgate SRAM is used as an example circuit. The baseline SRAM circuit is subjected to power minimization using a dual-VTh assignment based on a novel Design of(More)
In this paper, we present the design of a P4 (Power-Performance-Process-Parasitic) aware voltage controlled oscillator (VCO) at nano-CMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance (center frequency) of the VCO. For process variation analysis, we propose a methodology called Design(More)