Dhiraj K. Pradhan

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Transmission Control Protocol (TCP) assumes a relatively reliable underlying network where most packet losses are due to congestion. In a wireless network, however, packet losses will occur more often due to unreliable wireless links than due to congestion. When using TCP over wireless links, each packet loss on the wireless link results in congestion(More)
Motivated by the problem of test pattern generation in digital circuits, this paper presents a novel technique called recursive learning, able to perform a logic analysis on digital circuits. By recursively calling certain learning functions, it is possible to extract all logic dependencies between signals in a circuit and to perform precise implications(More)
The design and analysis of routing protocols is an important issue in dynamic networks such as packet radio and ad-hoc wireless networks. Most conventional protocols exhibit their least desirable behavior for highly dynamic interconnection topologies. We propose a new methodology for routing and topology information maintenance in dynamic networks. The(More)
The problem of achieving consensus in a distributed system is discussed. Systems are treated where either or both of two types of faults may occur: dormant (essentially omission and timing faults) and arbitrary (exhibits arbitrary behavior, commonly referred to as Byzantine). Previous results showed [7], [3], [4], [lo] that any number of dormant faults may(More)
Editorial Board Pattern Sensitivity in MOS Memories p. 2 Diagnostic Testing of MOS Random Access Memories p. 6 Testing Semiconductor Memories p. 11 What Is Necessary for Testing "ROMs" and "PROMs"? p. 26 Microprocessor Function Test Generation on the Sentry 600 p. 32 A Tutorial Paper on Software Approaches to Testing of Microprocessor Systems p. 41 Can a(More)
The original algorithm for the SAT problem, Variable Elimination Resolution (VER/DP) has exponential space complexity. To tackle that, the backtracking-based DPLL procedure [2] is used in SAT solvers. We present a combination of two techniques: we use NiVER, a special case of VER, to eliminate some variables in a preprocessing step, and then solve the(More)
Proposed here is a novel architecture for a fault-tolerant multiprocessor environment. It is assumed that the multiprocessor organization consists of a pool of active processing modules and either a small number of spare modules or active modules with some spare processing capacity. A fault-tolerance scheme is developed for duplex systems using checkpoints.(More)
A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The design methodology is circuit-specific and uses synthesis techniques to design BIST generators. The pattern generator consists of two components: a pseudorandom pattern generator (like an LFSR or, preferably, a GLFSR) and a combinational logic to map(More)
A new and effective pseudorandom test pattern generator, termed GLFSR, is introduced. These are linear feedback shift registers (LFSR’s) over a Galois field GF(2 ); ( > 1). Unlike conventional LFSR’s, which are over GF(2), these generators are not equivalent to cellular arrays and are shown to achieve significantly higher fault coverage. Experimental(More)