Dhiraj Goswami

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In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during atspeed ATPG has been presented in [1][2]. The new method has been applied to and tested on many example circuits at Semiconductor Technology(More)
Generating test patterns without considering timing exceptions and constraints can lead to invalid test responses, resulting in false failures on the tester or yield loss. A path-oriented approach to handle timing exception paths with setup violations during at-speed test generation has been presented in [1]. This paper presents a unified and complete(More)
The basic methodologies for creating at-speed test patterns are covered in numerous sources.2 While creating at-speed test patterns, it is important to account for timing exceptions and constraints such as false and multicycle paths. If these paths are not handled correctly during scan-based at-speed test pattern generation, it can lead to lower test(More)
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