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Emerging byte-addressable, non-volatile memory technologies offer performance within an order of magnitude of DRAM, prompting their inclusion in the processor memory subsystem. However, such load/store accessible Persistent Memory (<i>PM</i>) has implications on system design, both hardware and software. In this paper, we explore system software support to(More)
Heterogeneous architectures that integrate a mix of big and small cores are very attractive because they can achieve high single-threaded performance while enabling high performance thread-level parallelism with lower energy costs. Despite their benefits, they pose significant challenges to the operating system software. Thread scheduling is one of the most(More)
A heterogeneous processor consists of cores that are asymmetric in performance and functionality. Such a design provides a cost-effective solution for processor manufacturers to continuously improve both single-thread performance and multi-thread throughput. This design, however, faces significant challenges in the operating system, which traditionally(More)
Over the last decade, homogeneous multi-core processors emerged and became the de-facto approach for offering high parallelism, high performance and scalability for a wide range of platforms. We are now at an interesting juncture where several critical factors (smaller form factor devices, power challenges, need for specialization, etc) are guiding(More)
We present a sensor network simulation environment that allows users to evaluate the effects of different architectural choices and strategies on the lifetime and performance of a sensor network. Our tool can also be used to evaluate new approaches (routing protocols, cooperation algorithms), and compare them with the ones already in place. This simulator(More)
Network Simulation tools have played very significant role in wireless network research in the past decade. Compared to wired networks, there are a lot more parameters that effect the behavior of wireless networks. For reasons of simplicity and computational complexity, some details are abstracted out when implementing protocol models in network simulators.(More)
Heterogeneous multicore processors (HMPs), consisting of cores with different performance/power characteristics , have been proposed to deliver higher energy efficiency than symmetric multicores. This paper investigates the opportunities and limitations in using HMPs to gain energy-efficiency. Unlike previous work focused on server systems, we focus on the(More)
To my sister Susan Nadine Grizzard – A truly amazing person ACKNOWLEDGEMENTS Most importantly, I would like to deeply thank my advisor Dr. Henry Owen for his unparalleled brilliance and excellent guidance. His continuous encouragement and unwavering support have been of tremendous value to me. I would also like to thank my committee members Dr. Their(More)
The simulation of computer networks requires accurate models of user behavior. To this end, we present empirical models of end-user network traffic derived from the analysis of NETI@home data. There are two forms of models presented. The first models traffic for a specific TCP or UDP port. The second models all TCP or UDP traffic for an end-user. These(More)
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single-threaded performance coupled with high multi-threaded throughput and higher performance-per-watt. A significant portion of the commercial multicore heterogeneous processors are likely to have a common instruction set architecture( ISA). However,(More)