Deyun Cai

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<?Pub Dtl?>In this paper, low phase-noise, low-power, and compact oscillators are demonstrated at the millimeter-wave region based on differential transmission lines (DTLs) loaded with metamaterial resonators. There are two types of metamaterial resonators explored: split-ring resonators (SRRs) and complementary split-ring resonators (CSRRs). By creating a(More)
This paper has explored an ultra-low-power design of two 60-GHz direct-conversion receivers in a 65-nm CMOS process for single-channel and multi-channel applications under the IEEE 802.15.3c standard, respectively. One subthreshold biasing 0.4-V transconductance mixer is designed with a compact quadrature hybrid coupler (160 &#x03BC;m &#x00D7; 210 &#x03BC;m(More)
(2012). A dividerless PLL with low power and low reference spur by aperture-phase detector and phase-to-analog converter. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or(More)
A power and area efficient CMOS oscillator by high-Q metamaterial resonator is introduced in this paper for phase noise improvement. The resonator is based on the differential transmission-line (T-line) loaded with split ring resonator (SRR), which can enhance the EM energy coupling and further improve the Q. The proposed oscillator is implemented in 65-nm(More)
This paper presents a 8448MHz phase-locked loop (PLL) with a proposed divider implemented in 0.13 &#x00B5;m CMOS technology. Compared with conventional current mode logic (CML) divider, the proposed split-load divider presents wider operating frequency range and lower power dissipation. The ratio of the locking range over the center frequency is up to 70%(More)
This paper presents an improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications. The output signals of the proposed PFD have perfect symmetry with the additional four latches. Two small PMOS transistors and two inverters are added to work as level recovery to avoid the uncertain state of PFD when the(More)
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