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Recent work has illustrated the promise ofmultilevel approaches for partitioning large circuits. Multilevel partitioningrecursively clusters the instance until its size is smallerthan a given threshold, then unclusters the instance while applyinga partitioning refinement algorithm. Our multilevel partitioner usesa new technique to control the number of(More)
We study theminimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology Extended-DME (Ex-DME) extends the DME algorithm for exact zero-skew trees via the concept of(More)
A linear wirelength objective more eeectively captures timing , congestion, and other global placement considerations than a squared wirelength objective. The GORDIAN-L cell placement tool 16] minimizes linear wirelength by rst approximating the linear wirelength objective by a modiied squared wirelength objective, then executing the following loop { (1)(More)
Iterative improvement partitioning algorithms such as those due to Fiduccia and Mattheyses FM 22 and Krishnamurthy 55 exploit an eecient gain bucket data structure in selecting modules that are m o v e d f r om one partition to the other. In this paper, we investigate three gain bucket implementations and their eeect on the performance of the FM(More)
The "quadratic placement" methodology is rooted in [Module Placement Based on Resistive Network Optimization, Proud: A Sea-Of-Gate Placement Algorithm, A Combined Force and Cut Algorithm for Hierarchical VLSI Layout]and is reputedly used in many commercial and in-house tools forplacement of standard-cell and gate-array designs. The methodologyiterates(More)
We show how to quantify the suboptimality of heuristic algorithms for NP-hard problems arising in VLSI layout. Our approach is based on the notion of constructing new scaled instances from an initial problem instance. From the given problem instance, we essentially construct doubled, tripled, etc. instances which have optimum solution costs at most twice,(More)
Motivated by analysis of distributed R C delay in routing trees, we propose a new tree c onstruction for performance-driven global routing which directly trades oo between Prim's minimum spanning tree a l-gorithm and Dijkstra's shortest path tree algorithm. This direct combination of two objective functions and their corresponding optimal algorithms(More)
Top-down partitioning has focused on minimum cut or ratio cut objectives, while bottom-up clustering has focused on density-based objectives. In seeking a more unified perspective, we propose a new sum of densities measure for multi-way circuit decomposition, where the density of a subhypergraph is the ratio of the number of edges to the number of nodes in(More)
This paper considers the problem of partitioning a circuit into a collection of subcircuits, such that each subcircuit is feasible for some device from an FPGA library, and the total cost of devices is minimized. We propose a three-phase heuristic that uses ordering, clustering, and dynamic programming to achieve good solutions. Experimental comparisons are(More)