Denis Teixeira Franco

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Fault-tolerant design approaches have been studied as a possible solution for the expected reduction in the reliability of nanoscale integrated circuits. The increase in functional reliability, obtained with fault-tolerant design techniques, comes at a price, i.e., hardware or temporal redundancy. The resulting overhead can be justified in mission critical(More)
This paper deals with digital VLSI design aspects related to reliability. The focus is on the problem of reliability evaluation in combinational logic circuits. We present some methods for this evaluation that can be easily integrated in a tradidional design flow. Also we describe suitable metrics for performance estimation of concurrent error detection(More)