Denis Teixeira Franco

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0026-2714/$ see front matter 2008 Elsevier Ltd. A doi:10.1016/j.microrel.2008.07.002 * Corresponding author. Address: Institut TELECO CNRS, COMELEC Departement, 46 Rue Barrault, 75 0145817103; fax: +33 0145804036. E-mail address: denis.teixeira@telecom-paristech.f As integrated circuits scale down into nanometer dimensions, a great reduction on the(More)
Fault-tolerant design approaches have been studied as a possible solution for the expected reduction in the reliability of nanoscale integrated circuits. The increase in functional reliability, obtained with fault-tolerant design techniques, comes at a price, i.e., hardware or temporal redundancy. The resulting overhead can be justified in mission critical(More)
This paper deals with digital VLSI design aspects related to reliability. The focus is on the problem of reliability evaluation in combinational logic circuits. We present some methods for this evaluation that can be easily integrated in a tradidional design flow. Also we describe suitable metrics for performance estimation of concurrent error detection(More)
Integrated circuits have known a constant evolution in the last decades, with increases in density and speed that followed the rates predicted by Moore's law. The tradeo s in area, speed and power, allowed by the CMOS technology, and its capacity to integrate analog, digital and mixed components, are key features to the dissemination of integrated circuits(More)