Deepashree Sengupta

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This paper presents a method for inferring circuit delay shifts due to bias temperature instability using ring oscillator (ROSC) sensors. This procedure is based on presilicon analysis, postsilicon ROSC measurements, a new aging analysis model called the Upperbound on f<sub>Max</sub> (UofM), and a look-up table that stores a precomputed degradation ratio(More)
Fast delay estimation methods, as compared to simulation techniques, are needed for incremental performance-driven layout synthesis. On-chip inductive and conductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speeds; circuit complexity and interconnect lengths. Inductance causes noise in the signal(More)
Bias temperature instability (BTI) induced delay shifts in a circuit depend strongly on its operating environment. While sensors can capture some operating parameters, they are ineffective in measuring vital performance shifts due to changes in the workloads and signal probabilities. This paper determines the delay of an aged circuit by amalgamating more(More)
JPEG compression based on the discrete cosine transform (DCT) is a key building block in low-power multimedia applications. We use approximate computing to exploit the error tolerance of JPEG and formulate a novel optimization problem that maximizes power savings under an error budget. We analyze the error propagation sensitivity in the DCT network and use(More)
Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there are few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error(More)
A wide variety of error tolerant applications supports the use of approximate circuits that achieve power savings by introducing small errors. This paper proposes a fast and novel algorithm for the design of such circuits with the goal of maximizing power savings, constrained by a fixed error budget, through an analytical expression to optimally select the(More)
The performance of nanometer-scale circuits is adversely affected by aging induced by bias temperature instability (BTI) and hot carrier injection (HCI). Both BTI and HCI impact transistor electrical parameters at a level that depends on the operating environment and usage of the circuit. This paper presents a novel method, using on-chip sensors based on(More)
Over the years, there has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors and interconnects. The thrust to propagate these models to higher levels of abstraction to predict the reliability of larger circuits is much more recent. This paper addresses the intersection of(More)
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