Deepak M. Mathew

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Hybrid ARQ is being considered as a potential method for improving the performance of WCDMA in UMTS. In this paper, we compare different hybrid ARQ techniques, namely the incremental redundancy type I1 hybrid ARQ schemes and type I hybrid ARQ schemes with and without SOB combining. The emphasis is at high data rates and downlink shared channel (DSCH). Both(More)
Dynamic Random Access Memories (DRAM) have a big impact on performance and contribute significantly to the total power consumption in systems ranging from mobile devices to servers. Up to half of the power consumption of future high density DRAM devices will be caused by refresh commands. Moreover, not only the refresh rate does depend on the device(More)
In the context of approximate computing, <i>Approximate Dynamic Random Access Memory</i> (ADRAM) enables the tradeoff between energy efficiency, performance and reliability. The inherent error resilience of applications allows sacrificing data storage robustness and stability by lowering the refresh rate or disabling refresh in DRAMs completely.(More)
DRAM devices contribute significantly to the power consumption of today's computing systems. As the DRAM banks are getting denser, bank-wise power contribution is becoming more and more significant in modern DRAM devices. Therefore, DDR3 and LPDDR3/4 devices support Partial Array Self Refresh (PASR), while the latter and High Bandwidth Memory (HBM) provide(More)
The increasing gap between the bandwidth requirements of modern Systems on Chip (SoC) and the I/O data rate delivered by Dynamic Random Access Memory (DRAM), known as the Memory Wall, limits the performance of today's data-intensive applications. General purpose memory controllers use online scheduling techniques in order to increase the memory bandwidth.(More)
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