Debiprasanna Sahoo

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Concurrent execution of multiple applications on chip multiprocessors leads to interference at different level of shared resources like the banks of a DRAM. There are a few studies in literature suggest that we can dynamically partition the DRAM banks among the running processes. However, a detailed performance statistics is not available in existing(More)
The authors have developed a formal model based DRAM simulator called MSimDRAM. The authors start with the DRAM controller (DRAM-C) requirements. The authors next develop an architectural design in terms of interacting agents along with the constraints associated with each agent and its interface. Keeping the architecture in mind, they develop a formal(More)
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