Debesh Bhatta

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Measurement of the quality of tests run during high volume manufacturing of microprocessors is important to ensure desired outgoing product quality. For digital logic on die, such measurement is performed using techniques such as fast event-driven fault simulation using mature fault models such as stuck-at and transition faults. For analog modules on die,(More)
Jitter measurement is an essential part for testing high speed digital I/O and clock distribution networks. Precise jitter characterization of signals at critical internal nodes provides valuable information for hardware fault diagnosis and next generation design. Recently, incoherent undersampling has been proposed as a <i>low-cost solution</i> for signal(More)
This paper presents a 10-Gb/s coherent detection system incorporating feed-forward equalizers (FFEs) and an optical duobinary modulation scheme in order to increase the transmission distance limited by chromatic dispersion in standard single-mode fibers up to 400-km without signal regeneration and optical dispersion compensation. The FFE structure is based(More)
Modern high speed communication systems often employ both analog and digital blocks. This poses a challenge for simulation of closed loop system dynamics in presence of nonidealities in any of the analog blocks. Due the size and complexity of such systems it is not possible to do full system level simulation with circuit level models. The presence of(More)
Modern microprocessor pipelines experience timing uncertainties due to manufacturing process variations, thermal variations, supply voltage droop and data-dependent path delays. This leads to power and/or performance inefficiencies in current timing guard banding methods especially when pipeline stages are operating well under their critical path timing(More)