Debapriya Sahu

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This paper describes the PLL designed for the analog front-end of the silicon tuner in the cable modem system. The PLL is used to generate clocks (150-175MHz) for the DAC and hence the phase noise (jitter) requirement is very aggressive (15ps rms, which is less than 1 degree of integrated phase error). Low noise design for all the main blocks was a key to(More)
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