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After over 10 years of intensive study on high-k dielectric and metal gate electrode to replace silicon based materials (Si02 or SiON gate dielectric and polysilicon gate) in the complementary-metal-oxide-semiconductor (CMOS) application, it was claimed that hafnium based dielectric and metal gate are finally ready to be implemented in 45nm technology and(More)
A 3D trenched-structure metal-insulator-metal (MIM) nanocapacitor array with an ultrahigh equivalent planar capacitance (EPC) of ~300 μF cm(-2) is demonstrated. Zinc oxide (ZnO) and aluminum oxide (Al2O3) bilayer dielectric is deposited on 1 μm high biomimetic silicon nanotip (SiNT) substrate using the atomic layer deposition method. The large EPC is(More)
A single pulse technique with a wide range of pulse times has been applied to study trap charging and discharging mechanisms in nMOSFET high-k devices. It is shown that both charging and discharging are controlled by two distinctive processes with different characteristic times. A proposed characterization methodology, which separates the relaxation effects(More)
Band engineering in TANOS (TaN-Al<sub>2</sub>O<sub>3</sub>-Si<sub>3</sub>N<sub>4</sub>-SiO<sub>2</sub>-Silicon) Flash memory utilizing an interfacial dipole is demonstrated for the first time. A dipole layer at the tunnel oxide/charge storage layer interface leads to increase in programming speed while maintaining good retention and endurance. Using a(More)
— Test structures for accurate UHF capacitance –voltage (C-V) measurements of high performance CMOSFETs with Hf-based high-k dielectric and TiN metal gate are analyzed. It is shown that series resistance or substrate resistance between the channel region and body contact plays a role in UHF C-V measurements. The substrate resistance beneath the gate region(More)
Hole trap generation during positive bias temperature instability (PBTI) in nMOS high-k transistors is reported. It is suggested that the generation of these hole traps is associated with nitrogen species that mighty be incorporated in the gate stack through processes that contain nitrogen.
Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO<sub>2 </sub>/HfO<sub>2</sub>/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects(More)
High-k gate stack reliability has become one of the critical factors impacting the introduction of advanced gate stacks in future technology nodes. A high density of as-grown electron traps in the transition metal oxides (Bersuker et al., 2004) and the presence of the SiO<sub>2</sub> layer at the interface between the high-k dielectric and the substrate,(More)
We demonstrate for the first time a gate first high-k/metal gate (MG) nFET with EOT = 0.74 nm (T<sub>inv</sub> = 1.15 nm), low V<sub>t</sub> = 0.30 V, high performance [I<sub>on</sub>/I<sub>Off</sub> = 1310(muA/um) at 100(nA/um)], low leakage (&gt; 200x reduction vs. SiO<sub>2</sub>/PolySi) and good PBTI. Low-k interface layer scaling and high-k La-doping(More)