Davide Sabena

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• Modern generation of Multi-processor Systems-on-Chip (MP-SoCs) are increasingly sensitive to faults – Shrinking technology – Lower voltage margins • There is the need of accurate test solutions – Effective fault model – Fast elaboration • To provide a method for effectively evaluate the fault tolerance capability of Networks on Chip (NoCs)
Feature size reduction drastically influences permanent faults occurrence in nanometer technology devices. Among the various test techniques, Software-Based Self-Test (SBST) approaches have been demonstrated to be an effective solution for detecting logic defects, although achieving complete fault coverage is a challenging issue due to the functional-based(More)
—Reconfigurable architectures are increasingly employed in a large range of embedded applications, mainly due to their ability to provide high performance and high flexibility, combined with the possibility to be tuned according to the specific task they address. Reconfigurable systems are today used in several application areas, and are also suitable for(More)