This case study presents the results of porting a production scientific code, called NAMD, to the SRC-6 high-performance reconfigurable computing platform based on Field Programmable Gate Array (FPGA) technology. NAMD is a molecular dynamics code designed to run on large supercomputing systems and used extensively by the computational biophysics community.… (More)
This paper contains details on a project aimed to provide location-aware value-added services to the participants of an academic conference. The major characteristic of this project is the fusion of RFID technology, database management, data mining, real-time information visualization, and interactive web application technologies into an operational… (More)
The computer algorithm used to reconstruct CT scanner images is very computationally intensive, which forces medical equipment manufacturers to strike a balance among image resolution, image generation time, and system cost when designing a new CT scanner. Cost-effective performance acceleration for image reconstruction would allow manufacturers to generate… (More)
By design, the SRC-6 reconfigurable computer is programmed in the MAP C programming language within the framework provided by the SRC Carte™ development environment. The functionality of the original language can be extended via third party subroutines, called macros. These macros, typically implemented in Verilog Hardware Description Language, are brought… (More)
When comparing CPU based application performance to FPGA based application performance, we suggest that system dependant FPGA overhead time must be included in the comparison.
In this case study, a data-oriented approach is used to visualize a complex digital signal processing pipeline. The pipeline implements a Frequency Modulated (FM) Software-Defined Radio (SDR). SDR is an emerging technology where portions of the radio hardware, such as filtering and modulation, are replaced by software components. We discuss how an SDR… (More)
The Extensible Sensor Platform (ESP) combines a sensor bus with a Software Defined Radio (SDR). The first field programmable gate array (FPGA) implementation of the ESP supports the Phillips Semiconductors I 2 C sensor bus. The SDR provides the system with a programmable, flexible means of communicating sensor data over wireless data network available in a… (More)