David Neves

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This paper presents an innovative methodology to efficiently schedule design automation tasks during the execution of an analog IC layout-aware sizing process. The referred synthesis process includes several sub-tasks such as DC simulation, floorplanning, placement, global routing, parasitic extraction, and circuit simulations in multiple worst case(More)
This paper presents a methodology to increase the efficiency of automatic analog integrated circuit synthesis and optimization including simultaneously sizing; layout; and worst case corners, by using the multiple CPUs that are cheaply available in today's workstations. While most individual tools, for example circuit simulators already provide some sort of(More)
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