David M. Zar

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The Universal Serial Bus (USB) is now the ubiquitous interface bus of choice for connecting peripherals to personal computers and laptops. USB 2.0 is a half-duplex bus running at 480 Mb/s and each peripheral can draw as much as 500 mA of current at a nominal 5 V from the USB connector. We have developed a family of USB-based, B-mode probes that connect(More)
Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and below. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad(More)
Synchronizers are used to mitigate the effects of metastability in multiple clock domain System-on-Chip devices. In order to enable reliable synchronization, the synchronizer MTBF (Mean Time Between Failures) should be much longer than the product lifetime. To achieve such high margins, multistage synchronizers are used. Several simulation methods have been(More)
A low-cost PCI-bus-based ultrasound sub-system has been developed and integrated into the image-guided neurosurgery system currently in use at the Cleveland Clinic. Two software applications have been developed that integrate real-time ultrasound images with preoperative MR and CT data sets. By tracking the position of the ultrasound probe during surgery,(More)
Careful synchronizer design is imperative as System-on-Chip (SoC) products become prevalent in safety-critical applications. Previously, use of a flip-flop optimized for data applications was adequate for most synchronizer uses when laid out as a two-stage design. Increased demands for both reliability and low-power have exposed this two-stage solution to(More)
System-on-a-chip designs typically employ multiple clock domains to interface several externally clocked circuits operating at different frequencies and to reduce power and area by breaking large clock trees into multiple small ones. The principal challenge of such globally asynchronous locally synchronous architectures is the need to reliably communicate(More)
As the number of transistors on a single integrated circuit approach a billion, the problems of clock distribution, power consumption, multiple clock domains, meeting timing requirements, and reuse of subsystem designs grow ever more difficult. Coordinating a billion transistors with the present design methodologies will require hundreds of years of(More)
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