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—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook domino pipelines suffer significant timing overhead from clock skew, latch delay, and the inability to borrow time. To eliminate this overhead, some designers provide multiple overlapping clock phases such that domino gates are always ready for evaluation by the… (More)
SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the… (More)
Aesthetic plastic surgery has been long practiced for primarily psychological rather than physical benefit to patients. However, evaluation of the psychological impact of aesthetic plastic surgery has often been of limited methodological rigor in both study design and appropriate measurement. This study is intended to evaluate the psychological impact of… (More)
—Clock skew is an increasing concern for high-speed circuit designers. Circuit designers use transparent latches and skew-tolerant domino circuits to hide clock skew from the critical path and take advantage of shared portions of the clock network to budget less skew between nearby elements than across the entire die, but current timing analysis algorithms… (More)
OBJECTIVES To develop a psychometrically robust and widely applicable short form of the Derriford Appearance Scale, (DAS59), which (1) will reliably and validly assess the distress and difficulties experienced in living with problems of appearance, (2) is acceptable to clinical and non-clinical populations, and (3) facilitates research and clinical… (More)
This paper demonstrates all-optical 3R regeneration in 10-Gb/s NRZ field trials with various regeneration spacings up to 462 km. The 3R regenerator has achieved 1000-hop cascaded error-free transmission (total 66,000-km) without hop-to-hop power penalties.
This paper describes the input/output subsystem that is provided with the Hawk operating system kernel and the SANDAC V computer. Hawk and the SANDAC V were designed for embedded hard real-time applications. The IOS is a hierarchically organized set of modules t h a t can be configured to match the requirements of a specific real-time application. It was… (More)
A coustic energy can precisely and accurately eject a droplet of liquid from a reservoir, enabling delivery of picoliter and nanoliter volumes low nanoliter volumes between microplates using focused acousticsdautomation considerations. Acoustic droplet ejection has been shown to be extremely precise (coefficients of variation !2%) over a wide range of… (More)
We demonstrate field trial experiments to evaluate a 10-Gb/s optical 3R regenerator using fiber recirculation loops built with 264-km and 462-km SSMF fiber in field. Error-free transmission over 264,000-km with 1,000 optical 3R regeneration stages has been achieved. Experimental results indicate only 1.5-dB power penalty at BER 10-9 after 264,000-km.