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- Rajeev Alur, David L. Dill
- Theor. Comput. Sci.
- 1994

Alur, R. and D.L. Dill, A theory of timed automata, Theoretical Computer Science 126 (1994) 183-235. We propose timed (j&e) automata to model the behavior of real-time systems over time. Our definition provides a simple, and yet powerful, way to annotate state-transition graphs with timing constraints using finitely many real-valued clocks. A timed… (More)

- Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
- Inf. Comput.
- 1990

Many diierent methods have been devised for automatically verifying nite state systems by examining state-graph models of system behavior. These methods all depend on decision procedures that explicitly represent the state space using a list or a table that grows in proportion to the number of states. We describe a general method that represents the state… (More)

- Rajeev Alur, David L. Dill
- ICALP
- 1990

- Rajeev Alur, Costas Courcoubetis, David L. Dill
- Inf. Comput.
- 1993

- Cristian Cadar, Vijay Ganesh, Peter M. Pawlowski, David L. Dill, Dawson R. Engler
- ACM Conference on Computer and Communications…
- 2006

This article presents EXE, an effective bug-finding tool that automatically generates inputs that crash real code. Instead of running code on manually or randomly constructed input, EXE runs it on symbolic input initially allowed to be anything. As checked code runs, EXE tracks the constraints on each symbolic (i.e., input-derived) memory location. If a… (More)

- Vijay Ganesh, David L. Dill
- CAV
- 2007

STP is a decision procedure for the satisfiability of quantifier-free formulas in the theory of bit-vectors and arrays that has been optimized for large problems encountered in software analysis applications. The basic architecture of the procedure consists of word-level pre-processing algorithms followed by translation to SAT. The primary bottlenecks in… (More)

- Jerry R. Burch, David L. Dill
- CAV
- 1994

- David L. Dill, Andreas J. Drexler, Alan J. Hu, C. Han Yang
- ICCD
- 1992

The role of automatic formal protocol veriica-tion in hardware design is considered. Principles are identiied that maximize the beneets of protocol veriication while minimizing the labor and computation required. A new protocol description language and veriier (both called Mur') are described , along with experiences in applying them to two industrial… (More)

- David L. Dill
- Automatic Verification Methods for Finite State…
- 1989

- C. Norris Ip, David L. Dill
- CHDL
- 1993