David J. Rennie

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We propose a quad-node ten transistor (10T) soft error robust SRAM cell that offers differential read operation for robust sensing. The cell exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional soft error tolerant 12T DICE SRAM cell. When compared to a conventional 6T SRAM cell, the proposed cell offers similar(More)
The appropriate choice of flip-flop topologies is of essential importance in the design of integrated circuits for CMOS VLSI high-performance and high-speed circuits. The understanding of the suitability of the flip-flops and select the best topology for a given application is important to meet the need of the design to meet low power and high performance(More)
OBJECTIVES A review of the current literature is used to propose a 'conceptual model for relative pitch hardness' and how this may affect incidence of injury within Association Football. Based upon the injury risk and causation model of Meeuwisse et al. (Clin J Sport Med 2007; 17(3):215), it may provide researchers a necessary framework to guide future(More)
The synchronizer is constrained such that its state does not change when a latching operation fails. Therefore, any failed latching attempts are automatically retried in the subsequent cycles. For this we simulates the 8 bit multiplier, 4 bit 16 state finite state machine, 16 slot 8 bit data first in first out register etc. In a multi clock system,(More)
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