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The insight that firms may make “strategic investments” to alter future competitive conditions is one of the most fundamental ideas in industrial organization. Jean Tirole’s (1988) chapter reviewing arguments about how excess capacity, capital structure, advertising, contractual practices, learning-by-doing, and other actions can be used to deter entry is(More)
In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto(More)
This work discusses FPGA hardware implementations of all eSTREAM phase 3 hardware stream cipher candidates (profile 2) and some of their derivatives. The designs are optimized for maximum throughput per unit area as well as minimum area, and targeted for Xilinx Spartan 3 FPGAs. The results have found that the Grain and Trivium families of ciphers have(More)
An intriguing puzzle in cognitive neuroscience over recent years has been the common observation of parietal lobe activation in functional neuroimaging studies during the performance of human memory tasks. These findings have surprised scientists and clinicians because they challenge decades of established thinking that the parietal lobe does not support(More)
Security for sensor networks is challenging due to the resource-constrained nature of individual nodes, particularly their energy limitations. However, designing merely for energy savings may not result in a suitable security architecture. This paper investigates the inherent tradeoffs involved between energy, memory, and security robustness in distributed(More)
The security of sensor networks is a challenging area. Key management is one of the crucial parts in constructing the security among sensor nodes. However, key management protocols require a great deal of energy consumption, particularly in the transmission of initial key negotiation messages. In this paper, we examine three previously published sensor(More)
This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower resource usage than prior art. The 16-bit 1024-point FFT with the R22SDF architecture had(More)
Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm's mathematical security. Differential(More)
This thesis proposes a methodology to create an effective performance measurement system for an interconnected organization. The performance measurement system is composed of three components: a metrics set, a metrics review business process, and a dashboard visualization technique to display the data. If designed according to the proposed methodology, the(More)