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A compact modeling approach for silicon-chip slow-wave transmission lines with slotted bottom metal ground planes is studied and its limitations are presented. The modeling approach facilitates the calculation of the slow-wave transmission line parameters based upon the corresponding coplanar and grounded coplanar transmission-line parameters. The described(More)
In this paper, a distributed active transformer for the operation in the millimeter-wave frequency range is presented. The transformer utilizes stacked coupled wires as opposed to slab inductors to achieve a high coupling factor of k<sub>f</sub>=0.8 at 60 GHz. Scalable and compact equivalent-circuit models are used for the transformer design without the(More)
This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in [4], into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T line) devices for the critical interconnects, which is expanded to include coplanar(More)
This paper presents an on-chip, interconnect-awaremethodology for high-speed analog and mixed signal(AMS) design which enables early incorporation of on-chiptransmission line (T-line) components into AMS design flow.The proposed solution is based on a set of parameterizedT-line structures, which include single and two coupled microstriplines with optional(More)
This paper presents a wideband modeling methodology for on-chip coplanar single and coupled transmission lines over the conductive silicon substrate. Cost effective, semi analytical models have been developed, being purely based on explicit expressions. Silicon substrate induced loss and dispersion effects are considered, as well as the skin and proximity(More)
An analytic appraoch is presented for estimating the nonlinearity of an analog to digital converter (ADC) as a function of the variations in the circuit devices. The approach is demonstrated for the case of a pipeline ADC with digital error correction. Under some mild assumptions on the expected variations, the error probability is expressed as a simple(More)
A 25 GHz low noise amplifier using standard 0.18 mum digital CMOS technology is presented. Matching networks were based upon slow wave transmissions lines. Peak gain of 12.8 dB at 24 GHz and in-band minimum noise figure less than 4 dB were obtained at a power consumption of 8 mW. These record results demonstrate the usefulness of the slow wave transmission(More)
RF CMOS is gaining significant momentum as the technology of choice for implementing product designs in the 1-10GHz band. With scaling pushing f<sub>T</sub> and f<sub>MAX</sub> of FET's beyond 300GHz and integration of back-end-of-line (BEOL) conducive to low-loss passives, CMOS is poised to address application needs in the X, K and V bands
This paper presents an approach to physical design and modelling of Network-on-Chip Interconnects using on-chip transmission lines. Design guidelines are presented allowing the use of simple models with frequency-independent RLCG parameters. Circuit simulation results demonstrate the validity of this approach in a real design environment.
A simple design criterion is presented for obtaining maximal data rate in network on chip (NoC) links. It is shown that the maximal data rate is achieved near the boundary between RC and RLC model validity domains. The criterion is applicable to various on-chip transmission line structures, including crossing lines at adjacent metal layers. Inductive(More)
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