David Giuliano

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This paper presents a two-stage architecture that combines a large step-down switched-capacitor transformation stage with a high-bandwidth magnetic regulation stage. The proposed design is particularly well-suited for an integrated CMOS process, as it makes use of the available on-die device characteristics. In such a process, the two-stage architecture(More)
A fully monolithic interleaved buck dc-dc point-of-load (PoL) converter has been designed and fabricated in a 0.18-mm SiGe BiCMOS process. Target application of the design is 3-D power delivery for future microprocessors, in which the PoL converter will be vertically integrated with the processor using wafer-level 3-D interconnect technologies. Advantages(More)
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