David G. Bradlee

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To achieve high performance in uniprocessor RISC systems, compilers must perform both register allocation to reduce memory references and instruction scheduling to avoid pipeline hazards. Compilers that separate the two functions should perform poorly on uniprocessor RISCS that support multi-cycle operations, particularly on computation-intensive workloads.(More)
Marion is a retargetable code generator system designed specifically for RISCS. Each code generator is built from a machine description that includes code selection and code scheduling information in a concise and readable format. The description language is designed to be easy to use, yet rich enough to support a broad range of RISCS. We have used Marion(More)
This paper examines the effect of code generation strategy and register set size and structure on the performance of RISC processors. We vary the number of registers from 16 to 128, in both split and shared organizations, and use three different code generation strategies that differ in the way their instruction schedulers and register allocators cooperate(More)
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