We describe a method for using abstraction to reduce the complexity of temporal logic model checking. The basis of this method is a way of constructing an abstract model of a program without everâ€¦ (More)

We describe a framework for compositional verification of finite-state processes. The framework is based on two ideas: a subset of the logic CTL for which satisfaction is preserved under composition,â€¦ (More)

Integral equation techniques are often used to extract models of integrated circuit structures. This extraction involves solving a dense system of linear equations, and using direct solution methodsâ€¦ (More)

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDDâ€™s) [7] and partitioned trunsirion relationsâ€¦ (More)

A B S T R A C T : Temporal logic model checking is an automatic technique for verifying finite-state concurrent systems. Specifications are expressed in a propositional temporal logic, and theâ€¦ (More)

We describe a method for reducing the complexity of temporal logic model checking in systems composed of many parallel processes. The goal is to check properties of the components of a system andâ€¦ (More)

We significantly reduce the complexity of BDD-based symbolic verification by using partitioned transition relations to represent state transition graphs. On an example pipeline circuit, thisâ€¦ (More)

The fast integral equation solver presented here is ideal for three-dimensional problems with smooth, far-field kernels. IES3 solves electrostatic and electromagnetic problems in small circuitâ€¦ (More)