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We define an algorithmic paradigm, the stack model, that captures many primal-dual and local-ratio algorithms for approximating covering and packing problems. The stack model is defined syntactically and without any complexity limitations and hence our approximation bounds are independent of the <i>P</i> versus <i>NP</i> question. Using the stack model, we(More)
This paper describes the Altera Stratix II&#8482; logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance(More)
This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM(More)
This paper describes architectural enhancements in the Stratix-III" and Stratix-IV" FPGA architectures. These architectures feature programmable power management, which allows the power and performance of logic and routing to be varied to minimize total power without any performance loss. This paper describes the technique used for programmable power(More)
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