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High-level synthesis is the transformation from a behavioral level specification of hardware, through a series of optimizations and translations, to an implementation in terms of logic gates and registers. The success of a high-level synthesis system is heavily dependent on how effectively the high-level language captures the ideas of the designer in a(More)
Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, timing constraints and operations with unbounded delays, i.e. delays unknown at compile time, must also be(More)
| The scope of most high-level synthesis eeorts to date has been at the level of a single behavioral model represented as a control/data-ow graph. The communication between concurrently executing processes and its requirements in terms of timing and resources have largely been neglected. This restriction limits the applicability of most existing approaches(More)
Most approaches to control-unit optimization use a finite state machine model, where operations are bound to control states. However, when synthesizing circuits from a higher, more abstract level of hardware specification that supports concurrency and synchronization, these approaches may be overly restrictive. We present a strategy for optimizing control(More)
Most approaches to control optimization use a finite state machine model, where operations are bound to control states. However, when synthesizing circuits from a higher, more abstract level of hardware specification that supports concurrency and synchronization, these approaches may be overly restrictive. We present a strategy for optimizing control(More)