David Bañeres

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Variable-latency designs may improve the performance of those circuits in which the worst-case delay paths are infrequently activated. <i>Telescopic units</i> emerged as a scheme to automatically synthesize variable-latency circuits. In this paper, a novel approach is proposed that brings three main contributions with regard to the methods used for(More)
The synthesis of digital circuits is a basic skill in all the bachelor programmes around the ICT area of knowledge, such as Computer Science, Telecommunication Engineering or Electrical Engineering. An important hindrance in the learning process of this skill is that the existing educational tools for the design of circuits do not allow the student to(More)
In this paper we analyze three well-known preprocessors for Max-SAT. The first preprocessor is based on the so-called variable saturation. The second preprocessor is based on the resolution mechanism incorporated in modern branch and bound solvers. The third preprocessor is specific for the Maximum Clique problem and other problems with similar encoding in(More)
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis(More)
Assessment is an important part of the learning process. The instructor should be able to evaluate whether a learner has acquired the knowledge and competences provided in the course. Moreover, assessment activities also help a learner to check his level of expertise. Typically, the assessment model and assessment activities of subjects in official(More)
Even though online education is a very important pillar of lifelong education, institutions are still reluctant to wager for a fully online educational model. At the end, they keep relying on on-site assessment systems, mainly because fully virtual alternatives do not have the deserved social recognition or credibility. Thus, the design of virtual(More)
An approach for layout-aware interconnect optimization is presented. It is based on the combination of three sub-problems into the same framework: gate duplication, buffer insertion and placement. Different techniques to control the combinatorial explosion are proposed. The experimental results show tangible benefits in delay that endorse the suitability(More)
Learning digital systems design is a difficult skill that students of Bachelors on Computer Science, Electronic Engineering or Telecommunications have to acquire in the initial courses. The problem aggravates when the student is learning in a virtual environment with no face-to-face interaction with the instructor. In this case, simulators or intelligent(More)