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The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers. We leverage an existing full-system functional simulation infrastructure (Simics [14]) as the basis around which to build a set of timing simulator modules for modeling(More)
The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models.(More)
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes providing data version management for the simultaneous storage of both new (visible if the transaction commits) and old (retained if the transaction aborts) values. Most (hardware)(More)
Authors/Task Force Members: Giuseppe Mancia (Chairperson) (Italy)*, Robert Fagard (Chairperson) (Belgium)*, Krzysztof Narkiewicz (Section co-ordinator) (Poland), Josep Redon (Section co-ordinator) (Spain), Alberto Zanchetti (Section co-ordinator) (Italy), Michael Böhm (Germany), Thierry Christiaens (Belgium), Renata Cifkova (Czech Republic), Guy De Backer(More)
This paper proposes a hardware transactional memory (HTM) system called LogTM Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transactions read-and write-sets and detects conflicts on coherence requests (eager conflict detection). Transactions update memory "in place" after saving the old value in a per-thread memory log (eager version(More)
In response to increasing (relative) wire delay, architects have proposed various technologies to manage the impact of slow wires on large uniprocessor L2 caches. Block migration (e.g., D-NUCA and NuRapid) reduces average hit latency by migrating frequently used blocks towards the lower-latency banks. Transmission Line Caches (TLC) use on-chip transmission(More)
Cardiovascular disease (CVD) due to atherosclerosis of the arterial vessel wall and to thrombosis is the foremost cause of premature mortality and of disability-adjusted life years (DALYs) in Europe, and is also increasingly common in developing countries.1 In the European Union, the economic cost of CVD represents annually E192 billion1 in direct and(More)
Modern processors use two or more levels ofcache memories to bridge the rising disparity betweenprocessor and memory speeds. Compression canimprove cache performance by increasing effectivecache capacity and eliminating misses. However,decompressing cache lines also increases cache accesslatency, potentially degrading performance.In this paper, we develop(More)
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques should help database applications, which are becoming increasingly compute and memory bound. Unfortunately, recent studies report that faster processors do not improve database(More)
We develop an availability solution, called <i>SafetyNet,</i> that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At an abstract level, <i>SafetyNet</i> logically maintains multiple, globally consistent checkpoints of the state of a shared memory multiprocessor (i.e., processors, memory,(More)