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The next-generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64b Haswell cores, 45MB L3 cache, 4 DDR4-2133MHz memory channels, 40 8GT/s PCIe lanes, and 60… Continue Reading
The next generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64 bit Haswell cores, 45 MB L3 cache, 4 DDR4-2133 MHz memory channels, 40 8 GT/s PCIe lanes, and… Continue Reading
This paper presents a 2.5-16 Gbps Gen4 PCIe transceiver with 3-tap Tx EQ, and 8-tap Rx DFE in a 10nm FinFET CMOS technology. A low latency digital CDR is designed supporting a flexible timing… Continue Reading
Underwater low-frequency sound can travel great distances in the oceans, and sound triggered in the sea by the mechanical energy transfer from the Earth's crust (e.g., earthquakes or volcanoes) and… Continue Reading
The NASA Goddard Space Flight Center (GSFC) Small Explorer (SMEX) mission operations team is currently involved in reengineering the Mission Operations Center (MOC) to infuse new software… Continue Reading