Daryoosh Dideban

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A novel simulation algorithm capable of capturing statistical variability manifests in digital design is proposed. The only estimations for the algorithm inputs are the standard deviations of channel length and the gate voltage. Implementing the algorithm for the simulation of propagation delay times of the basic digital building blocks such as inverter,(More)
Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model parameter extraction for the new industry standard compact model PSP, we(More)
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