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A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the(More)
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is(More)
Due to the inconsistent effects of human immunodeficiency virus (HIV) on the human male reproduction in previous studies and the impacts of environmental exposures, such as heavy metals, on male reproduction receiving little attention in HIV-infected population, the aim of present study was to investigate whether heavy metals have potential effects on(More)
A novel design scheme using neuron-MOS dynamic literal circuit and double pass-transistor logic(DPL), to realize voltage-mode dynamic ternary logic gate, is proposed. The double pass-transistor used to transmit ternary signal is controlled by the output of the dynamic literal circuit to realize ternary logic function. The complementarity and duality(More)
A new true-single-phase clocked (TSPC) full-adder using floating-gate MOS (FGMOS) transistor is presented. In this new design scheme, the logic tree for the sum-generate circuit is realized using only an n-channel multiple-input FGMOS transistor, and the logic for the carry-generate circuit is realized using a complementary FGMOS-based inverter. By using(More)
Two new differential flip-flops using neuron-MOS transistors are presented, including one-latch single edge-triggered(IL-SET) flip-flop and one-latch double edge-triggered(IL-DET) flip-flop. In the new differential flip-flops, a pair of n-channel neuron-MOS transistors is used to replace the nMOS logic tree in the conventional differential flip-flops. The(More)
A new enhanced dynamic logic using multiple-input floating-gate MOS(FGMOS) transistors is presented. The circuit technique is designed using an n-channel multiple-input FGMOS pull down logic tree instead of the nMOS logic tree in the conventional enhanced differential cascode voltage switch logic (EDCVSL) circuit. The logic tree of EDCVSL is dramatically(More)
A novel Schmitt trigger with controllable hysteresis using neuron-MOS transistors is presented. By selecting the ratio of capacitive coupling coefficients, a Schmitt trigger with different hysteresis characteristics can be achieved. By only varying the external input control signals, the hysteresis window can be conveniently moved without changing its(More)