Danyan Zhang

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A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the(More)
To obtain the maximum power drew from the photovoltaic (PV) array as well as to control small power PV systems more easily and conveniently, a novel analog voltage-based maximum power point tracking control IC was proposed in this paper. Not only is the IC involved in tracking the maximum power point (MPP) of the PV array, but it also renews the value of(More)
A novel Schmitt trigger with controllable hysteresis using neuron-MOS transistors is presented. By selecting the ratio of capacitive coupling coefficients, a Schmitt trigger with different hysteresis characteristics can be achieved. By only varying the external input control signals, the hysteresis window can be conveniently moved without changing its(More)
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is(More)
A novel voltage-mode CMOS ternary Schmitt trigger using neuron-MOS transistors is presented. By controlling the voltages of the multiple-input gates, the neuron-MOS literal circuits with hysteresis characteristics are firstly designed. Then, the transmission switches used to pass ternary signal are controlled by the outputs of the literal circuits to(More)
Two new differential flip-flops using neuron-MOS transistors are presented, including one-latch single edge-triggered(IL-SET) flip-flop and one-latch double edge-triggered(IL-DET) flip-flop. In the new differential flip-flops, a pair of n-channel neuron-MOS transistors is used to replace the nMOS logic tree in the conventional differential flip-flops. The(More)
A new enhanced dynamic logic using multiple-input floating-gate MOS(FGMOS) transistors is presented. The circuit technique is designed using an n-channel multiple-input FGMOS pull down logic tree instead of the nMOS logic tree in the conventional enhanced differential cascode voltage switch logic (EDCVSL) circuit. The logic tree of EDCVSL is dramatically(More)
A No Race (NORA) dynamic logic using neuron-MOS transistor is presented. The circuit is designed using the n-channel neuron-MOS transistor instead of the nMOS logic block or pMOS logic block in the conventional NORA dynamic logic circuit. The proposed full-adder shows that the logic block of NORA circuit can be simplified by utilizing neuron-MOS transistor.(More)
A new true-single-phase clocked (TSPC) full-adder using floating-gate MOS (FGMOS) transistor is presented. In this new design scheme, the logic tree for the sum-generate circuit is realized using only an n-channel multiple-input FGMOS transistor, and the logic for the carry-generate circuit is realized using a complementary FGMOS-based inverter. By using(More)
A novel design scheme using neuron-MOS dynamic literal circuit and double pass-transistor logic(DPL), to realize voltage-mode dynamic ternary logic gate, is proposed. The double pass-transistor used to transmit ternary signal is controlled by the output of the dynamic literal circuit to realize ternary logic function. The complementarity and duality(More)