Daniele D. Caviglia

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In this paper we present a VHDL-based design methodology which we adopted in the design of an ASIC chip for real time image analysis in a quality control industrial environment. The design methodology is based on the following considerations: i) we explored the design space by applying some high level transformations on the VHDL specications; ii) we dened(More)
| In this paper we present a three layer hierarchical neural network architecture to be used in early vision processing tasks (e.g. texture segregation). Taking into account both the linear properties of simple cells receptive elds and the non-linear properties of intracortical processing , we deened the structure and the function-ality of simple, complex(More)
This paper presents a new neural network approach to the pre-placement of VLSI blocks. Our innovation consists in considering the pre-placement problem as a classification problem, and in implementing a neural network learning algorithm, derived from Kohonen maps, to accomplish this task. The neural network has been simulated and the results have been(More)